74C14 HEX SCHMITT TRIGGER

Hex Inverting Schmitt Trigger (6-gate inverter chip with hysteresis).
This chip is often considered the heart of Nv net technology, since each Schmitt inverter is individually-accessible (and so each, along with a capacitor, can be turned into a Nv neuron).

The MM74C14 Hex Schmitt Trigger is a monolithic comple-
mentary MOS (CMOS) integrated circuit constructed with
N- and P-channel enhancement transistors. The positive
and negative going threshold voltages VT+ and VT−, show
low variation with respect to temperature (typ. 0.0005V/°C
at VCC = 10V), and hysteresis, VT
+− VT−≥ 0.2VCC is guar-
anteed.

All inputs are protected from damage due to static dis-
charge by diode clamps to VCC and GND.

■Wide supply voltage range: 3.0V to 15V
■High noise immunity: 0.70 V
CC (typ.)
■Low power: TTL compatibility:
0.4 VCC (typ.) 0.2 VCC guaranteed
■Hysteresis: 0.4 V
CC (typ.): 0.2 VCC guaranteed

4017 DECADE COUNTER
GENERAL DESCRIPTION
The 74HC/HCT4017 are high-speed Si-gate CMOS
devices and are pin compatible with the “4017” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4017 are 5-stage Johnson decade
counters with 10 decoded active HIGH outputs (Q0 to Q9),
an active LOW output from the most significant flip-flop
(Q5-9), active HIGH and active LOW clock inputs (CP0 and
CP1) and an overriding asynchronous master reset input
(MR).
The counter is advanced by either a LOW-to-HIGH
transition at CP0 whileCP1 is LOW or a HIGH-to-LOW
transition at CP1 while CP0 is HIGH (see also function
table).
When cascading counters, theQ5-9 output, which is LOW
while the counter is in states 5, 6, 7, 8 and 9, can be used
to drive the CP0 input of the next counter.
A HIGH on MR resets the counter to zero
(Q0=Q5-9=HIGH; Q1 to Q9=LOW) independent of the
clock inputs (CP0 andCP1).
Automatic code correction of the counter is provided by an
internal circuit: following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
FEATURES
• Output capability: standard
• ICC category: MSI

4046 VCO CHIP
GENERAL DESCRIPTION
The 74HC/HCT4046A are high-speed Si-gate CMOS
devices and are pin compatible with the “4046” of the
“4000B” series. The 74HC/HCT4046A are phase-locked-loop circuits that
comprise a linear voltage-controlled oscillator (VCO) and
three different phase comparators (PC1, PC2 and PC3)
with a common signal input amplifier and a common
comparator input.

The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input
amplifiers. With a passive low-pass filter, the “4046A”
forms a second-order loop PLL. The excellent VCO
linearity is achieved by the use of linear op-amp
techniques.